References

논문 원문을 저장소에 무단 재배포하지 않고 DOI와 공식 출판사 페이지로 연결합니다.

Core references

1. S. Mukesh and J. Zhang, “A Review of the Gate-All-Around Nanosheet FET Process Opportunities,” Electronics 11(21), 3589 (2022).
   DOI: https://doi.org/10.3390/electronics11213589
   연구 역할: GAA nanosheet의 multi-Vt 요구, WFM modification/volume control, 제한된 sheet 간 공간과 WFM variability의 근거.

2. Sanjay, B. Prasad, and A. Vohra, “Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length,” Semiconductors 54, 1490-1495 (2020).
   DOI: https://doi.org/10.1134/S1063782620110111
   연구 역할: CGAA에서 DM gate와 control-gate length 변화가 DIBL에 미치는 영향의 직접 근거.

3. J. Zhang et al., “High-k Metal Gate Fundamental Learning and Multi-Vt Options for Stacked Nanosheet Gate-All-Around Transistor,” IEDM (2017).
   DOI: https://doi.org/10.1109/IEDM.2017.8268438
   연구 역할: stacked nanosheet에서 WFM thickness와 inter-sheet spacing을 활용한 multi-Vt 및 HKMG 배경.

4. Sanjay, V. Kumar, and A. Vohra, “Performance Comparison Between Inversion Mode and Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using Dual Metal Gate Work Function Engineering for Upcoming Sub 5 nm Technology Node,” Silicon 16, 989-1003 (2024).
   DOI: https://doi.org/10.1007/s12633-023-02730-x
   연구 역할: 5 nm CGAA 3D TCAD에서 dual-metal work-function engineering의 DIBL/SS/Ion-Ioff 비교 근거.

5. H. Arimura et al., “Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration,” IEEE VLSI Technology and Circuits (2024).
   DOI: https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631442
   연구 역할: 최신 GAA/CFET에서 gate-stack engineering을 통한 Vt fine-tuning의 근거.

6. B.-W. Huang et al., “WNxCy VT Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 VT Match / Improved 0.24 V Noise Margin / Record Gain of 61 V/V,” IEDM (2024).
   DOI: https://doi.org/10.1109/IEDM50854.2024.10873325
   연구 역할: dual-WFM split-gate nanosheet CFET의 실제 integration과 circuit-level benefit 근거.

7. Y.-Q. Liu et al., “VT Tuning of Split-Gate GeSi Nanosheet CFETs With Dual Work Function Metals,” IEEE Transactions on Electron Devices 72(9), 4708-4713 (2025).
   DOI: https://doi.org/10.1109/TED.2025.3592634
   연구 역할: PEALD WNxCy effective-work-function 조절과 split-gate CFET Vt tuning의 최신 실증 근거.

8. Sanjay, V. Kumar, and A. Vohra, “Quadruple Metal Gate Work Function Engineering to Enhance DC and Analog/RF Performance in Junctionless Cylindrical GAA Si Nanowire MOSFET at Sub 3 nm Technology Node,” Silicon 17, 4675-4686 (2025).
   DOI: https://doi.org/10.1007/s12633-025-03494-2
   연구 역할: sub-3 nm CGAA에서 multiple-metal WFM 연구가 지속되는 최신 동향의 보조 근거.

9. J. Robertson and R. M. Wallace, “High-K Materials and Metal Gates for CMOS Applications,” Materials Science and Engineering: R: Reports 88, 1-41 (2015).
   DOI: https://doi.org/10.1016/j.mser.2014.11.001
   연구 역할: ultrathin SiO₂ tunneling, physically thicker high-K dielectric, interface/band-offset/reliability 배경.

Evidence classification

• References 2, 4, 8: TCAD/simulation evidence
• References 6, 7: actual CFET integration evidence
• References 1, 3, 5, 9: process, gate-stack, and technology-context evidence

본 프로젝트의 2D planar 결과는 GAA/CFET 양산 공정을 실증한 결과가 아니라, 복잡한 3D 구조로 확장하기 전 Work-Function Split의 물리적 방향성을 분리 검증한 concept study입니다.

Official technology context

• TSMC, N2 Technology — official nanosheet technology context: https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm
• Samsung Electronics, 3 nm GAA production announcement: https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture
• ASML, What is a gate-all-around transistor: https://www.asml.com/en/news/stories/2022/what-is-a-gate-all-around-transistor
• TU Wien, Drain-Induced Barrier Lowering: https://www.iue.tuwien.ac.at/phd/stockinger/node15.html

Use in this portfolio

문헌은 최신 gate-stack/WFM 연구 맥락과 후속 연구 방향을 설정하는 데 사용했습니다. 본 프로젝트의 수치 결과는 업로드된 Sentaurus simulation data에서만 제시하며, 문헌 결과와 직접 동일시하지 않습니다.